Semiconductor process simulation is the modeling of the fabrication of semiconductor devices such as transistors. It is used as an alternative to physically taking cross sections of the semiconductor devices for quality analysis. A goal of process simulation is an accurate prediction of device geometry, active dopant distribution, stress distribution, etc. Process simulation is conventionally used as an input for device simulation, the modeling of device electrical characteristics.
The fabrication of integrated circuit devices requires a series of processing steps called a process flow. Process simulation involves modeling all essential steps in the process flow in order to obtain dopant and stress profiles and, to a lesser extent, device geometry. The input for process simulation is the process flow and a layout. The layout is selected as a linear cut in a full layout for a two-dimensional (2D) simulation or a rectangular cut from the layout for a 3D simulation.
2D simulation has limitation relating to parameter inputs and is used for the design of the semiconductor devices, but not used for the manufacture of the semiconductor devices. Moreover, 2D simulation approaches fail to capture risks associated with inter- or intra-layer spacing in semiconductor patterns due to limitations of process window space.
A need therefore exists for methodology and an apparatus for generating a yield score that factors in both design and manufacturing to arrive at a risk factor based on realistic 3D simulation of semiconductor patterns.